Sensor Apparatus

ABSTRACT

The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.

TECHNICAL FIELD

The present invention relates to a sensor apparatus including a plurality of sensor elements.

BACKGROUND ART

In sensor apparatuses including a plurality of sensor elements, voltage values corresponding to the detection result of the amount of sensing by the respective sensor elements are outputted from a signal processing circuit, and further digital values corresponding to the voltage values are outputted from an A/D conversing circuit. Then, one- or two-dimensional distribution of the amount of sensing (e.g. light intensity, temperature, displacement) is obtained based on the digital values corresponding to the amount of sensing for the respective sensor elements. As an example of such a sensor apparatus, there can be cited an image pickup apparatus including a plurality of photodiodes that are arranged one- or two-dimensionally (refer to Patent Document 1).

Patent Document 1: Japanese Patent Application Laid-Open No. H9-51476

DISCLOSURE OF THE INVENTION Problem to be Solved by the Invention

The inventors have studied conventional sensor apparatuses in detail, and as a result, have found problems as follows. That is, the amount of sensing detected by such a sensor apparatus as described above may include not only a signal component that is supposed to be detected but also a noise component (disturbing light component, background light component) that is superimposed on the signal component. When the noise component (disturbing light component, background light component) is significantly indefinite, the A/D conversing circuit requires 10-bit outputted digital values for inputted voltage values with noise components (disturbing light components, background light components) superimposed on signal components, though 8-bit outputted digital values would suffice for, for example, inputted voltage values including signal components only, to A/D-convert the signal components with an accuracy equivalent to the 8-bit case.

When the outputted digital value of the A/D conversing circuit has a large number of bits, the A/D conversing circuit results in a long conversion time, large power consumption, and large circuit scale. It is generally necessary to A/D-convert the detection result of the amount of sensing by all sensor elements within a certain time period, which may require parallel processing using a plurality of A/D conversing circuits, resulting in a larger power consumption and larger circuit scale.

In order to overcome the above-mentioned problems, it is an object of the present invention to provide a sensor apparatus capable of obtaining digital values of signal components with a high accuracy, even in the case of the amount of sensing with noise components (disturbing light components, background light components) superimposed on the signal components, using an A/D conversing circuit with the outputted digital value thereof having a small number of bits.

Means for Solving Problem

A sensor apparatus according to the present invention comprises a sensor array section, a difference operating section, and an A/D converting section. In a first aspect of the sensor apparatus, the sensor array section includes N sensor elements (N represents an integer of 2 or more) and outputs a voltage value V_(n) in response to the result of sensing by the n-th sensor element (“n” represents any integer of 1 or more but N or less) among the N sensor elements. The difference operating section receives N voltage values V₁ to V_(N) outputted from the sensor array section and outputs a voltage value U_(n) (n≠1) corresponding to the difference (V_(n)−V_(n-1)) between voltage values V_(n) and V_(n-1). The A/D converting section receives the voltage value U_(n) outputted from the difference operating section, converts the voltage value U_(n) into a digital value, and then outputs the converted digital value.

In the sensor apparatus according to the above-described first aspect, the A/D converting section may converts at least one voltage value among the N voltage values V₁ to V_(N) into a digital value, and then outputs the converted digital value.

Also, in a second aspect of the sensor apparatus, the difference operating section may receives N voltage values V₁ to V_(N) outputted from the sensor array section and outputs a voltage value W_(n) corresponding to the difference (V_(n)−V_(n0)) between a specific voltage value V_(n0) and the voltage value V_(n) among the N voltage values V₁ to V_(N). In this case, the A/D converting section receives the voltage value W_(n) outputted from the difference operating section, converts the voltage value W_(n) into a digital value, and then outputs the converted digital value.

In the sensor apparatus according to the above-described second aspect, the A/D converting section may converts the specific voltage value V_(n0) into a digital value, and then outputs the converted digital value.

The sensor apparatus according to the present invention preferably further includes a holding section that receives the N voltage values V₁ to V_(N) outputted from the sensor array section and once holds the N voltage values V₁ to V_(N). In this case, the difference operating section outputs the voltage value U_(n) or W_(n) based on the N voltage values V₁ to V_(N) held by the holding section.

In the sensor apparatus according to the present invention, each of the N sensor elements preferably includes a photodiode. In this case, the one- or two-dimensional intensity distribution of incident light can be detected. Also, even when the intensity of incident light may include signal components and noise components (disturbing light components, background light components) and the noise components (disturbing light components, background light components) may be significantly indefinite, it is possible to obtain digital values of the signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits.

The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only and are not to be considered as limiting the present invention.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will be apparent to those skilled in the art from this detailed description.

EFFECT OF THE INVENTION

In accordance with the sensor apparatus according to the present invention, it is possible to obtain digital values of signal components with a high accuracy, even in the case of the amount of sensing with noise components (disturbing light components, background light components) superimposed on the signal components, using an A/D conversing circuit with the outputted digital value thereof having a small number of bits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing the overall configuration of a sensor apparatus according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram including a photodiode PD_(n), an integrating circuit 11 _(n), a CDS circuit 12 _(n), and a holding circuit 21 _(n) in the sensor apparatus according to the first embodiment;

FIG. 3 is a timing chart for explaining the operation of a difference operating section and an A/D converting section in the sensor apparatus according to the first embodiment;

FIG. 4 is a view showing the intensity distribution of light to be detected by the sensor apparatus according to the first embodiment;

FIG. 5 is a view showing the overall configuration of a sensor apparatus according to a second embodiment of the present invention; and

FIG. 6 is a circuit diagram of an APS circuit included in each pixel, showing the partial configuration of a sensor apparatus according to a modified example of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

-   -   1, 2 . . . sensor apparatuses; 10 . . . sensor array section; 11         . . . integrating circuit; 12 . . . CDS circuit; 20 . . .         holding section; 30, 30A . . . difference operating sections; 33         . . . subtracting circuit; and 40 . . . A/D converting section.

BEST MODES FOR CARRYING OUT THE INVENTION

In the following, embodiments of a sensor apparatus according to the present invention will be explained in detail with reference to FIGS. 1 to 6. In the explanation of the drawings, constituents identical to each other will be referred to with numerals identical to each other without repeating their overlapping descriptions.

First Embodiment

First, a sensor apparatus according to a first embodiment of the present invention will be explained. FIG. 1 is a view showing the overall configuration of the sensor apparatus according to the first embodiment of the present invention. The sensor apparatus 1 shown in FIG. 1 comprises a sensor array section 10, a holding section 20, a difference operating section 30, and an A/D converting section 40.

The sensor array section 10 includes N photodiodes PD₁ to PD_(N), N integrating circuits 11 ₁ to 11 _(N), and N CDS circuits 12 ₁ to 12 _(N). Also, the holding section 20 includes N holding circuits 21 ₁ to 21 _(N). Each of the photodiodes PD₁ to PD_(N) has a common composition, each of the integrating circuits 11 ₁ to 11 _(N) also has a common composition, each of the CDS circuits 12 ₁ to 12 _(N) also has a common composition, and each of the holding circuits 21 ₁ to 21 _(N) also has a common composition. The N photodiodes PD₁ to PD_(N) are arranged one-dimensionally. The n-th integrating circuit 11 _(n), n-th CDS circuit 12 _(n), and n-th holding circuit 21 _(n) are provided correspondingly to the n-th photodiode PD_(n). Here, N represents an integer of 2 or more. Also, “n” represents any integer of 1 or more but N or less, unless otherwise specified.

The photodiode PD_(n) generates electric charges corresponding to the amount of incident light and outputs the electric charges to the integrating circuit 11 _(n). Each integrating circuit 11 _(n) accumulates the electric charges outputted from the photodiode PD_(n) into a capacitive element and outputs a voltage value corresponding to the amount of accumulated charge to the CDS circuit 12 _(n). The CDS circuit 12 _(n) receives the voltage value outputted from the integrating circuit 11 _(n) and outputs a voltage value corresponding to the change of the inputted voltage value after a reference time based on the inputted voltage value at the reference time to the holding circuit 21 _(n). That is, the sensor array section 10 includes the N photodiodes PD₁ to PD_(N) as sensor elements and outputs a voltage value corresponding to the detection result of light by the photodiode PD_(n). The holding circuit 21 _(n) receives the voltage value outputted from the CDS circuit 12 _(n) and outputs the voltage value V_(n) held therein.

The difference operating section 30 includes switches SW_(31,1) to SW_(31,N), switches SW_(32,0) to SW_(32,N-1), and a subtracting circuit 33. The output terminal of the holding circuit 21 _(n) is connected to a wiring L1 via the switch SW_(31,n) and to a wiring L2 via the switch SW_(32,n). However, the output terminal of the N-th holding circuit 21 _(N) is connected to the wiring L1 via the switch SW_(31,N) but may not be connected to the wiring L2 via a switch. Also, the wiring L2 is connected with the ground potential via the switch SW_(32,0). The switches SW_(31,n) and SW_(32,n-1) open and close based on the level of a control signal S_(n). The subtracting circuit 33 outputs a voltage value corresponding to the difference between voltage values to be inputted through the respective wirings L1 and L2.

The A/D converting section 40 is used together with switches SW₄₁ and SW₄₂. The A/D converting section 40 receives one of a voltage value V_(FS1) to be inputted via the switch SW₄₁ and a voltage value V_(FS2) to be inputted via the switch SW₄₂ as a full scale in A/D conversion. Then, the A/D converting section 40 converts the voltage value outputted from the subtracting circuit 33 into a digital value at a resolution of one 2^(M)-th of the full scale (voltage value V_(FS1) or V_(FS2)), and then outputs the converted digital value. It is noted that M represents the number of bits of the outputted digital value. It is preferable that the voltage value V_(FS1) is greater than V_(FS2) and the ratio therebetween be a power of two. The switch SW₄₁ opens and closes based on the level of a control signal Sel1, while the switch SW₄₂ opens and closes based on the level of a control signal Sel2.

FIG. 2 is a circuit diagram including a photodiode PD_(n), an integrating circuit 11 _(n), a CDS circuit 12 _(n), and a holding circuit 21 _(n) in the sensor apparatus 1 according to the first embodiment. The anode terminal of the photodiode PD_(n) is grounded, while the cathode terminal thereof is connected to the input terminal of the integrating circuit 11 _(n), and the photodiode PD_(n) generates electric charges corresponding to the amount of incident light and outputs the electric charges to the integrating circuit 11 _(n).

The integrating circuit 11 _(n) includes an amplifier A₁₁, a capacitive element C₁₁, and a switch SW₁₁. The input terminal of the amplifier A₁₁ is connected to the cathode terminal of the photodiode PD_(n). The capacitive element C₁₁ and switch SW₁₁ are provided between the input and output terminals of the amplifier A₁₁ by being connected parallel with each other. The outputted voltage value of the integrating circuit 11 _(n) is initialized by closing the switch SW₁₁ so that the capacitive element C₁₁ is discharged. The integrating circuit 11 _(n) also accumulates electric charges outputted from the photodiode PD_(n) into the capacitive element C₁₁ when the switch SW₁₁ is opened, and then outputs a voltage value corresponding to the amount of accumulated charge to the CDS circuit 12 _(n).

The CDS circuit 12 _(n) includes an amplifier A₁₂, a capacitive element C₁₂, and a switch SW₁₂. The input terminal of the amplifier A₁₂ is connected to the amplifier A₁₁ in the integrating circuit 11 _(n) via the capacitive element C₁₂ and is grounded via the switch SW₁₂. The CDS circuit 12 _(n) receives the voltage value outputted from the integrating circuit 11 _(n) and outputs a voltage value corresponding to the change of the inputted voltage value after a reference time (when the switch SW₁₂ is opened) based on the inputted voltage value at the reference time from the amplifier A₁₂ to the holding circuit 21 _(n).

The holding circuit 21 _(n) includes an amplifier A₂₁, a capacitive element C₂₁, and a switch SW₂₁. The input terminal of the amplifier A₂₁ is connected to the amplifier A₁₂ in the CDS circuit 12 _(n) via the switch SW₂₁ and is grounded via the capacitive element C₂₁. The output terminal of the amplifier A₂₁ is connected to the wiring L1 via the switch SW_(31,n) and to the wiring L2 via the switch SW_(32,n). The holding circuit 21 _(n) holds the voltage value, which is outputted from the CDS circuit 12 _(n) at a time when the switch SW₂₁ is opened, in the capacitive element C₂₁ also after the time of the state variation, and then outputs a voltage value V_(n) corresponding to the held voltage value from the amplifier A₂₁.

The operation of the photodiode PD_(n), integrating circuit 11 _(n), CDS circuit 12 _(n), and holding circuit 21 _(n) is as follows.

That is, when the switch SW₁₁ in the integrating circuit 11 _(n) is opened, electric charges outputted from the photodiode PD_(n) are accumulated into the capacitive element C₁₁, and then a voltage value corresponding to the amount of accumulated charge is outputted from the integrating circuit 11 _(n). As the amount of charge accumulated in the capacitive element C₁₁ increases gradually, the voltage value outputted from the integrating circuit 11 _(n) varies. While the switch SW₁₁ in the integrating circuit 11 _(n) is opened, the switch SW₁₂ in the CDS circuit 12 _(n) is opened at a first time, and then the switch SW₂₁ in the holding circuit 21 _(n) is opened at a second time. The voltage value outputted from the CDS circuit 12 _(n) after the first time corresponds to the change of the voltage value outputted from the integrating circuit 11 _(n) based on the voltage value outputted from the integrating circuit 11 _(n) at the first time. Then, the voltage value V_(n) held by the holding circuit 21 _(n) after the second time corresponds to the voltage value outputted from the CDS circuit 12 _(n) at the second time.

That is, the voltage value V_(n) held by the holding circuit 21 _(n) after the second time corresponds to the difference between the voltage values outputted from the integrating circuit 11 _(n) at the first and second time, and when the time difference between the first and second time is constant, corresponds to the intensity of light incident to the photodiode PD_(n). It is noted that the N integrating circuits 11 ₁ to 11 _(N) operate at the same timing; the N CDS circuits 12 ₁ to 12 _(N) also operate at the same timing; and the N holding circuits 21 ₁ to 21 _(N) also operate at the same timing. Therefore, a voltage value V_(n) corresponding to the amount of incident light to the photodiode PD_(n) during a common period of time is to be held by the holding section 20.

Next, the operation of the difference operating section 30 and the A/D converting section 40 in the sensor apparatus 1 according to the first embodiment will be explained. FIG. 3 is a timing chart for explaining the operation of the difference operating section 30 and the A/D converting section 40 in the sensor apparatus 1 according to the first embodiment. FIG. 3 shows a timing chart when the difference operating section 30 and A/D converting section 40 process voltage values V₁ to V_(N) are held by the holding section 20 as described above. It is noted that not only the above-described operation of the sensor array section 10 and holding section 20 but also the operation of the difference operating section 30 and A/D converting section 40 to be explained hereinafter is performed based on various control signals outputted from a control section (not shown in the figures). FIG. 3 shows the level of each control signal S_(n) to be inputted to the difference operating section 30, the level of a control signal Sel1 for instructing the switch SW₄₁ to open and close, and the level of a control signal Sel2 for instructing the switch SW₄₂ to open and close in this order from the top.

As shown in FIG. 3, the control signals S₁ to S_(N) are made high sequentially. During the time period T_(n) from time t_(n,1) to time t_(n,2), only the control signal S_(n) is made high among the control signals S₁ to S_(N). During the time period T₁, the control signal Sel1 is made high, while the control signal Sel2 is made low. Also, from the time period T₂ through the time period T_(N), the control signal Sel1 is made low, while the control signal Sel2 is made high.

During the time period T₁ from time t_(1,1) to time t_(1,2), only the control signal S₁ is made high among the control signals S₁ to S_(N), so that the switches SW_(31,1) and SW_(32,0) in the difference operating section 30 are closed. Also, the control signal Sel1 is made high, so that the switch SW₄₁ is closed. When the switch SW_(31,1) is closed, the voltage value V₁ held by the holding circuit 21 ₁ is inputted to the subtracting circuit 33 through the switch SW_(31,1) and the wiring L1. Also, when the switch SW_(32,0) is closed, the ground potential is inputted to the subtracting circuit 33 through the switch SW_(32,0) and the wiring L2. In the subtracting circuit 33, the ground potential is subtracted from the voltage value V₁, and the subtracted voltage value V₁ is outputted. Then, in the A/D converting section 40, the voltage value V₁ outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value V_(FS1) inputted through the switch SW₄₁ as a full scale.

During the time period T_(n) from time t_(n,1) to time t_(n,2) (n≠1), only the control signal S_(n) is made high among the control signals S₁ to S_(N), so that the switches SW_(31,n) and SW_(32,n-1) in the difference operating section 30 are closed. Also, the control signal Sel2 is made high, so that the switch SW₄₂ is closed. When the switch SW_(31,n) is closed, the voltage value V_(n) held by the holding circuit 21 _(n) is inputted to the subtracting circuit 33 through the switch SW_(31,n) and the wiring L1. Also, when the switch SW_(32,n-1) is closed, the voltage value V_(n-1) held by the holding circuit 21 _(n-1) is inputted to the subtracting circuit 33 through the switch SW_(32,n-1) and the wiring L2. In the subtracting circuit 33, the voltage value V_(n-1) is subtracted from the voltage value V_(n), and a voltage value U_(n) corresponding to the subtraction result is outputted. Then, in the A/D converting section 40, the voltage value U_(n) outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value V_(FS2) inputted through the switch SW₄₂ as a full scale.

That is, during the time period T₁, the A/D converting section 40 converts the voltage value V₁ corresponding to the amount of incident light to the first photodiode PD₁ into an M-bit digital value using the voltage value V_(FS1) as a full scale. Also, during each time period T_(n) (n≠1), the difference operating section 30 calculates a voltage value U_(n) according to the difference (V_(n)−V_(n-1)) between voltage values V_(n) and V_(n-1) that correspond to the amount of incident light to the respective photodiodes PD_(n) and PD_(n-1), and then the A/D converting section 40 converts the voltage value U_(n) into an M-bit digital value using the voltage value V_(FS2) as a full scale.

Therefore, as shown in FIG. 4, even when significant noise components (disturbing light components, background light components) may be superimposed on signal components that are supposed to be detected in the intensity distribution of light to be detected by the sensor apparatus 1, the sensor apparatus 1 can obtain digital values of the signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40.

That is, the maximum value of the difference (V_(n)−V_(n-1)) between two adjacent voltage values V_(n) and V_(n-1) among the voltage values V₁ to V_(N) outputted from the respective holding circuits 21 ₁ to 21 _(N) is smaller than the maximum value of the voltage values V₁ to V_(N). Hence, the voltage value V_(FS2) to be used by the A/D converting section 40 as a full scale during the time period T_(n) (n≠1) is set to the maximum value of the difference (V_(n)−V_(n-1)) (or a value somewhat greater than the maximum value) or to the difference between the maximum and minimum values of signal components included in the voltage values V₁ to V_(N) (or a value somewhat greater than the difference). Thus, in the A/D converting section 40, the voltage value V_(FS2) to be used as a full scale is set appropriately and a voltage value U_(n) corresponding to the difference (V_(n)−V_(n-1)) is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents signal components with a high accuracy, though having a small number of bits of M.

Meanwhile, the maximum value of the voltage values V₁ to V_(N) outputted from the respective holding circuits 21 ₁ to 21 _(N) is larger. Hence, the voltage value V_(FS1) to be used by the A/D converting section 40 as a full scale during the time period T₁ is set to the maximum value of the voltage values V₁ to V_(N) (or a value somewhat greater than the maximum value) that is greater than the voltage value V_(FS2). Thus, in the A/D converting section 40, the voltage value V_(FS1) to be used as a full scale is set appropriately and the voltage value V₁ is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents the sum of signal components and noise components (disturbing light components, background light components), though having a small number of bits of M.

As described heretofore, the sensor apparatus 1 according to the first embodiment can obtain digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40. Therefore, the A/D converting section 40 results in a short conversion time, small power consumption, and small circuit scale. Also, even in the case of performing A/D conversion processing in parallel due to the requirement of performing the A/D conversion processing within a certain time period, the number of A/D converting sections for the parallel processing may be small, which also results in a small power consumption and small circuit scale.

Second Embodiment

Next, a sensor apparatus according to a second embodiment of the present invention will be explained. FIG. 5 is a view showing the overall configuration of the sensor apparatus according to the second embodiment of the present invention. The sensor apparatus 2 shown in FIG. 5 comprises a sensor array section 10, a holding section 20, a difference operating section 30A, and an A/D converting section 40. As compared with the configuration of the sensor apparatus 1 according to the above-described first embodiment (FIGS. 1 and 2), the sensor apparatus 2 according to the second embodiment is different from the first embodiment in that the difference operating section 30A is provided instead of the difference operating section 30.

The difference operating section 30A includes switches SW_(31,1) to SW_(31,N), switches SW_(32,0) and SW_(32,1), and a subtracting circuit 33. The output terminal of the holding circuit 21 _(n) is connected to a wiring L1 via the switch SW_(31,n). The output terminal of the first holding circuit 21 ₁ is connected to a wiring L2 via the switch SW_(32,1). Also, the wiring L2 is connected with the ground potential via the switch SW_(32,0). The switch SW_(31,n) opens and closes based on the level of a control signal S_(n), and the switch SW_(32,0) opens and closes based on the level of a control signal Sel1, while the switch SW_(32,1) opens and closes based on the level of a control signal Sel2. The subtracting circuit 33 outputs a voltage value corresponding to the difference between voltage values to be inputted through the respective wirings L1 and L2.

Next, the operation of the difference operating section 30A and the A/D converting section 40 in the sensor apparatus 2 according to the second embodiment will be explained. The timing chart for explaining the operation of the difference operating section 30A and the A/D converting section 40 in the sensor apparatus 2 according to the second embodiment is the same as in FIG. 3.

During the time period T₁ from time t_(1,1) to time t_(1,2), only the control signal S₁ is made high among the control signals S₁ to S_(N), so that the switch SW_(31,1) in the difference operating section 30A is closed. Also, the control signal Sel1 is made high, so that the switches SW_(32,0) and SW₄₁ are closed. When the switch SW_(31,1) is closed, the voltage value V₁ held by the holding circuit 21 ₁ is inputted to the subtracting circuit 33 through the switch SW_(31,1) and the wiring L1. Also, when the switch SW_(32,0) is closed, the ground potential is inputted to the subtracting circuit 33 through the switch SW_(32,0) and the wiring L2. In the subtracting circuit 33, the ground potential is subtracted from the voltage value V₁, and the subtracted voltage value V₁ is outputted. Then, in the A/D converting section 40, the voltage value V₁ outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value V_(FS1) inputted through the switch SW₄₁ as a full scale.

During the time period T_(n) from time t_(n,1) to time t_(n,2) (n≠1), only the control signal S_(n) is made high among the control signals S₁ to S_(N), so that the switch SW_(31,n) in the difference operating section 30A is closed. Also, the control signal Sel2 is made high, so that the switch SW₄₂ is closed. When the switch SW_(31,n) is closed, the voltage value V_(n) held by the holding circuit 21 _(n) is inputted to the subtracting circuit 33 through the switch SW_(31,n) and the wiring L1. Also, when the switch SW_(32,1) is closed, the voltage value V₁ held by the holding circuit 21 ₁ is inputted to the subtracting circuit 33 through the switch SW_(32,1) and the wiring L2. In the subtracting circuit 33, the voltage value V₁ is subtracted from the voltage value V_(n), and a voltage value W_(n) corresponding to the subtraction result is outputted. Then, in the A/D converting section 40, the voltage value W_(n) outputted from the subtracting circuit 33 is converted into an M-bit digital value using the voltage value V_(FS2) inputted through the switch SW₄₂ as a full scale.

That is, during the time period T₁, the A/D converting section 40 converts the voltage value V₁ corresponding to the amount of incident light to the first photodiode PD₁ into an M-bit digital value using the voltage value V_(FS1) as a full scale. Also, during the time period T_(n) (n≠1), the difference operating section 30A calculates a voltage value W_(n) corresponding to the difference (V_(n)−V₁) between voltage values V_(n) and V₁ that correspond to the amount of incident light to the respective photodiodes PD_(n) and PD₁, and then the A/D converting section 40 converts the voltage value W_(n) into an M-bit digital value using the voltage value V_(FS2) as a full scale.

Therefore, as shown in FIG. 4, even when significant noise components (disturbing light components, background light components) may be superimposed on signal components that are supposed to be detected in the intensity distribution of light to be detected by the sensor apparatus 2, the sensor apparatus 2 can obtain digital values of the signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40.

That is, the maximum value of the voltage value W_(n) to be obtained by a difference operation from the voltage values V₁ to V_(N) outputted from the respective holding circuits 21 ₁ to 21 _(N) is smaller than the maximum value of the voltage values V₁ to V_(N). Hence, the voltage value V_(FS2) to be used by the A/D converting section 40 as a full scale during the time period T_(n) (n≠1) is set to the maximum value of the voltage value W_(n) (or a value somewhat greater than the maximum value) or to the difference between the maximum and minimum values of signal components included in the voltage values V₁ to V_(N) (or a value somewhat greater than the difference). Thus, in the A/D converting section 40, the voltage value V_(FS2) to be used as a full scale is set appropriately and a voltage value W_(n) corresponding to the difference (V_(n)−V₁) is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents signal components with a high accuracy, though having a small number of bits of M.

Meanwhile, the maximum value of the voltage values V₁ to V_(N) outputted from the respective holding circuits 21 ₁ to 21 _(N) is larger. Hence, the voltage value V_(FS1) to be used by the A/D converting section 40 as a full scale during the time period T₁ is set to the maximum value of the voltage values V₁ to V_(N) (or a value somewhat greater than the maximum value) that is greater than the voltage value V_(FS2). Thus, in the A/D converting section 40, the voltage value V_(FS1) to be used as a full scale is set appropriately and the voltage value V₁ is converted into a digital value. Therefore, the digital value to be outputted from the A/D converting section 40 represents the sum of signal components and noise components (disturbing light components, background light components), though having a small number of bits of M.

As described above, the sensor apparatus 2 according to the second embodiment can obtain digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of bits of M as the A/D converting section 40. Therefore, the A/D converting section 40 results in a short conversion time, small power consumption, and small circuit scale. Also, even in the case of performing A/D conversion processing in parallel due to the requirement of performing the A/D conversion processing within a certain time period, the number of A/D converting sections for the parallel processing may be small, which also results in a small power consumption and small circuit scale.

(Exemplary Variation)

The present invention is not restricted to the above-described first and second embodiments, and various modifications may be made. For example, although the sensor apparatuses according to the above-described first and second embodiments are image pickup apparatuses including a plurality of photodiodes that are arranged one-dimensionally, the sensor apparatus according to the present invention may be an image pickup apparatus including a plurality of photodiodes that are arranged two-dimensionally. Further, the sensor apparatus according to the present invention may be an imaging apparatus in which each pixel includes an APS (Active Pixel Sensor) circuit shown in FIG. 6 as well as a plurality of photodiodes and the pixels are arranged one- or two-dimensionally. Also, the sensor apparatus according to the present invention is not restricted to an image pickup apparatus, but may include a plurality of sensor elements for detecting the amount of another sensing parameter (e.g. temperature, displacement).

From the invention thus described, it will be obvious that the embodiments of the invention may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended for inclusion within the scope of the following claims.

INDUSTRIAL APPLICABILITY

The sensor apparatus according to the present invention is applicable to, for example, an image pickup apparatus including a plurality of photodiodes that are arranged one- or two-dimensionally. 

1. A sensor apparatus comprising: a sensor array section including N sensor elements (N represents an integer of 2 or more) and outputting a voltage value V_(n) in response to the result of sensing by the n-th sensor element (“n” represents any integer of 1 or more but N or less) among said N sensor elements; a difference operating section outputting a voltage value U_(n) (n≠1) corresponding to the difference (V_(n)−V_(n-1)) between the voltage values V_(n) and V_(n-1) among N voltage values V₁ to V_(N) outputted from said sensor array section; and an A/D converting section converting the voltage value U_(n) outputted from said difference operating section into a digital value.
 2. A sensor apparatus according to claim 1, wherein said A/D converting section converts at least one voltage value of the N voltage values V₁ to V_(N) into a digital value.
 3. A sensor apparatus according to claim 1, further comprising a holding section once holding the N voltage values V₁ to V_(N) outputted from said sensor array section, and wherein said difference operating section outputs the voltage value U_(n) based on the N voltage values V₁ to V_(N) held by said holding section.
 4. A sensor apparatus according to claim 1, wherein each of said N sensor elements includes a photodiode.
 5. A sensor apparatus comprising: a sensor array section including N sensor elements (N represents an integer of 2 or more) and adapted to output a voltage value V_(n) in response to the result of sensing by the n-th sensor element (“n” represents any integer of 1 or more but N or less) among said N sensor elements; a difference operating section outputting a voltage value W_(n) corresponding to the difference (V_(n)−V_(n0)) between a specific voltage value V_(n0) and the voltage value V_(n) among N voltage values V₁ to V_(N) outputted from said sensor array section; and an A/D converting section converting the voltage value W_(n) outputted from said difference operating section into a digital value.
 6. A sensor apparatus according to claim 5, wherein said A/D converting section converts the specific voltage value V_(n0) into a digital value.
 7. A sensor apparatus according to claim 5, further comprising a holding section once holding the N voltage values V₁ to V_(N) outputted from said sensor array section, and wherein said difference operating section outputs the voltage value W_(n) based on the N voltage values V₁ to V_(N) held by said holding section.
 8. A sensor apparatus according to claim 5, wherein each of said N sensor elements includes a photodiode. 